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DOS Diagnostics

Introduction
Prerequisites
Functions List
Function Description
Diagnostic Tests
Error Messages

Introduction

This document provides the information on how to use the DOS diagnostic utilities program on Broadcom NetXtreme™ Gigabit Ethernet Controller, in particular BCM5788 and its related components.

Commands can be entered from DOS prompt or the Command Line Interface (CLI), prompt. Otherwise, the parameter is used as an executable command then exits the program. See the Function List section for a list of commands that can be entered from the DOS prompt and CLI.

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Prerequisites

OS:	Dos 6.22
Software:	5703.bin b57udiag.exe CONFIG.SYS cpu.bin cpu05.bin cpudg05.bin cpudiag.bin CPUMEM.BIN DIAGCFG.BIN flshdg05.bin FLSHDIAG.BIN

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Functions List

Type b57udiag -cmd to display the following information:

In CLI, assuming there are three devices in the system, all device information always displays before each prompt as seen in the following example:

C Brd:Rv    Bus   PCI Spd Base Irq EEP     MAC          Fmw     Configuration
- ------- ------- --- --- ---- -- ---- ------------ ----------- --------------
0 5788:A3 02:0A:0 32  33  FEAF  3 128K 0010180416DB 5788-v3.01  PW,auto
1 5788:A3 02:0B:0 32  33  FEAD 11 128K 0010180416C4 5788-v3.01  PW,auto
2 5788:A3 02:0C:0 32  33  FEAB  9 128K 0010180416B6 5703-v2.21  PW,auto 

Note that P and S stand for Primary and Secondary ports on the 5788.

cmd	Functions
upgfrm	Upgrade PXE or Boot Code from a file
dir	Display the file directory in NVRAM
setwol	Enable/Disable WOL
setpxe	Enable/Disable PXE
setasf	Enable/Diable ASF
nictest	Run a set of NIC tests
exit	Exit the program
device	Show or switch device
version	Display program version
help	Display the commands available
dos	Execute a DOS command
reset	Reset chip
cls	Clear screen
asfprg	Program ASF firmware into NVRAM

From the DOS prompt, the following options can be used with the commands:

Usage: A:\B57UDIAG.EXE [options]

cmd	Functions
-c <num>	Specify the card to be tested
-cmd	Enter command mode
-w <value>	Enable/Disable (value = 1/0) WOL in manufacture mode
-mba <value>	Option to enable/disable MBA 0 = Disable 1 = Enable
-mbap <value>	Option to select MBA protocol 0 = PXE 1= RPL 2 = BOOTP
-mbas <value>	Option to select MBA speed 0 = auto 1 = 10HD 2 = 10FD 3 = 100HD 4 = 100FD
-firm <file>	Update devices eeprom based on <file> image match

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Functions Description

upgfrm

cmd: upgfrm

Description: Upgrade PXE or Boot Code from a file

Syntax: upgrm <pxe:boot> filename

This command reads code from a file and programs it into the PXE or boot area. Both parameters, the programming target pxe or boot and filename must be specified.

Options:
-f <string>	Input file
-p	Upgrade PXE code
-b	Upgrade Boot code
-d	Do not perform device check

dir

cmd: dir

Description: Displays the file directory in NVRAM

Example:

Entry Type SRAM    Addr EEP  Offset     Length   Execute Version 
----- ------------ --------- ---------- -------- ------- ------- 
       BootCode    08003000  00000200   000011B0 CPUA (2) 5702-v2.24a        
  0    PXE         00010000  000013B0   0000C854 no       2.2.7

setwol

cmd: setwol

Description: Enable/Disable WOL.

Syntax: setwol -e/-d

Options:
-e	Enable WOL
-d	Disable WOL

setpxe

cmd: setpxe

Description: Enable/Disable PXE and set PXE speed.

Syntax: setpxe -switch

Options:
-e	Enable PXE
-d	Disable PXE
-s<DEC>	Specify PXE speed (default = 0)
	Speed: 0 = auto 1 = 10HD 2 = 10FD 3 = 100HD 4 = 100FD

setasf

cmd: setasf

Description: Enable/Disable ASF.

Syntax: setasf -switch

Options:
-e	Enable ASF
-d	Disable ASF

nictest

cmd: nictest

Description: Run a set of NIC tests.

Syntax: nictest [test list]

Example: See Diagnostic Tests for detail on test description.

abcd	runs all tests
b	runs all tests in group b
a3 b1	runs test a3 and b1 only
a124b2	runs tests a1, a2, a4 and b2

If no test list is entered, the diagcfg setting is used.

Options:
-n <DEC>	iteration
-e	run NVRAM verification also

exit

version

cmd: version

Description: Display software version.

Syntax: version

Example:

C:\>b57udiag –version
Copyright (c) 2000, 2001, 2002, 2003 Broadcom Corporation, all rights reserved
Broadcom NetXtreme User Diagnostic 3.09 (06/14/02)

help

cmd: help

Description: Displays the help commands available.

Syntax: help

Example:

C:\>b57udiag –help
Copyright (c) 2000, 2001, 2002, 2003 Broadcom Corporation, all rights reserved
Broadcom NetXtreme User Diagnostic 3.09 (06/14/02)

cmd	Functions
upgfrm	Upgrade PXE or Boot Code from a file
dir	Display the file directory in NVRAM
setwol	Enable/Disable WOL
setpxe	Enable/Disable PXE
setasf	Enable/Disable ASF
nictest	Run a set of NIC tests
exit	Exit the program
device	Show or switch device
version	Display program version
help	Display the commands available
dos	Execute a DOS command
reset	Reset chip
cls	Clear screen
asfprg	Program ASF firmware into NVRAM

dos

asfprg

cmd: asfprg

Description: Program asf firmware into NVRAM

Syntax: asfprg [init_img [rx_img [tx_img]]]

The default files names are asfinit.bin, asfcpua.bin, and asfcpub.bin, which can be over written by parameters.

Options:
-v<HEX>	Verbose level (0,1,2) (def=00000001)

 

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Diagnostic Tests

The tests are divided into four groups: Register Tests, Memory Tests, Miscellaneous Tests, and Data Tests. They are numbered as group A, B, C, and D.

Test Names

Group A.

A1. Indirect Register Test
A2. Control Register Test
A3. Interrupt Test
A4. BIST
A5. PCI Cfg Register Test

Group B.

B1. Scratch Pad Test
B2. BD SRAM Test
B3. DMA SRAM Test
B4. MBUF SRAM Test
B5. MBUF SRAM via DMA Test
B6. External SRAM Test

Group C.

C1. EEPROM Test
C2. CPU Test
C3. DMA Test
C4. MII Test
C5. VPD Test
C6. Alert Standard Format (ASF) Test
C7. ROM Expansion Test

Group D.

D1. Mac Loopback Test
D2. Phy Loopback Test
D3. RJ45 Loopback Test
D4. MII Miscellaneous Test
D5. MSI Test

Test Descriptions

A1. Indirect Register Test

Function: Using indirect addressing method, writing increment data into MAC hash Register table and read back for verification. The memory read/write is done 100 times while increment test data.

Default: Test Enabled

A2. Control Register Test

Function: Each Register specified in the configuration contents read only bit and read/write bit defines. The test writing zero and one into the test bits to insure the read only bits are not changed, and read/write bits are changed accordingly.

Default: Test Enabled.

A3. Interrupt Test

Function: This test verifies the interrupt functionality. It enables interrupt and waits for interrupt to occur. It waits for 500 ms and reports error if could not generate interrupts.

Default: Enabled

A4. BIST

Function: Hardware built-In-self-test (BIST). This test initiates BIST and waits for the test result returned by hardware.

Default: Because of the potential for intermittent failure, this test is currently disabled by default

A5. PCI Cfg Register Test

Function: This test verifies the access integrity of the PCI config registers.

B1. Scratch Pad Test

Function: This test tests the scratch pad SRAM on board. The following tests are performed:

Data Pattern Test: This test writes test data to the SRAM and reads it back to ensure that the data is correct. The test data used is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and 0x55AA55AA.

Alternate Data Pattern Test: This test writes test data into the SRAM, writes complement test data to the next address, and reads back both to ensure the data is correct. After the test, the program reads back data one more time to ensure that the data is still correct. The test data used is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and 0x55AA55AA.

Address Test: This test writes each address with a unique increment of data and reads back data to ensure data is correct. After filling the entire address with the unique data, the program reads back the data again to ensure that the data is still correct.

WalkingOne bit Test: For each address, data one is written and read back for testing. Then it shifts the data left one bit, so the data becomes two and repeats the same test. It repeats the test 32 times until the test bit is shifted out of the test address. The same test is repeated for entire test range.

Pseudo Random Data Test: A precalculated pseudo-random data set is used to write unique data to each test RAM. After passing the test, the program reads back the data one more time to ensure that the data is still correct.

Default: Enabled

B2. BD SRAM Test

Function: This test tests the BD SRAM. This performs exact the same way of testing as described in B1. Scratch Pad Test.

Default: Enabled

B3. DMA SRAM Test

Function: It tests DMA SRAM by performing the tests described in test B1. The Scratch Pad Test.

Default: Enabled

B4. MBUF SRAM Test

Function: It tests MBUF SRAM by performing the tests described in test B1. The Scratch Pad Test.

Default: Enabled

B5. MBUF SRAM via DMA Test

Function: Eight test pattern data are used in the test. They are described below. A 0x1000 sized data buffer is used for this test. Before each pattern test, the buffer is initialized and filled with the test pattern. It then, performs size 0x1000 transmit DMA from host buffer to NIC MBUF memory. Verify the data integrity in MBUF against host memory and repeat the DMA for the entire MBUF buffer. Then it performs receive DMA from NIC to host. The 0x1000-byte test buffer is cleared to zero before each receive-DMA. Verify the data integrity and test is repeated for the entire MBUF SRAM range.

Test Pattern	Description
16 00s 16 FFs	Full the entire host DMA buffer with 16 bytes of 00s and then 16 bytes of FFs.
16 FFs 16 0s	Full the entire host DMA buffer with 16 bytes of FFs and then 16 bytes of 00s.
32 00s 32 FFs	Full the entire host DMA buffer with 32 bytes of 00s and then 32 bytes of FFs.
32 FFs 32 00s	Full the entire host DMA buffer with 32 bytes of FFs and then 32 bytes of 00s.
00000000s"	Full the entire host DMA buffer with all zeros.
FFFFFFFFs	Full the entire host DMA buffer with all FFs.
AA55AA55s	Full the entire host DMA buffer with data 0xAA55AA55.
55AA55AAs	Full the entire host DMA buffer with data 0x55AA55AA.

Default: Enabled

B6. External SRAM Test

Function: It tests External SRAM by performing the tests described in test B1. The Scratch Pad Test.

Default: Disabled

C1. EEPROM Test

Function: An increment test data is used in EEPROM test. It fills the test data into the test range and read back to verity the content. After the test, it fills data with zero to clear the memory.

Default: Enabled

C2. CPU Test

Function: This test opens the file cpu.bin. If file exists and content is good, it loads code to rx and tx CPU and verifies CPU execution.

Default: Enabled

C3. DMA Test

Function: Both high and low priorities DMA are tested. It moves data from host memory to NIC SRAM, verifies data, and then moves data back to host memory again to verify data.

Default: Enabled

C4. MII Test

Function: The function is identical to A2. Control Register Test. Each Register specified in the configuration contents read only bit and read/write bit defines. The test writing zero and one into the test bits to insure the read only bits value are not changed, and read/write bits are changed accordingly.

Default: Test Enabled.

Default Register table

The test will try to read the register configuration file ‘miireg.txt’ for the register defines. If the file does not exists, the following table is used:

Offset 		R/O Mask	R/W Mask
0x00 		0x0000 		0x7180 
0x02 		0xffff 		0x0000 
0x03 		0xffff 		0x0000 
0x04 		0x0000 		0xffff 
0x05 		0xefff 		0x0000 
0x06 		0x0001 		0x0000 
0x07 		0x0800 		0xb7ff 
0x08 		0xffff 		0x0000 
0x09 		0x0000 		0xff00 
0x0a 		0x7c00 		0x0000 
0x10 		0x0000 		0xffbf 
0x11 		0x3300 		0x0000 
0x19 		0x001f 		0x0000 
0x1e 		0x0000 		0xffff 
0x1f 		0x0000 		0xffff 

C5. VPD Test

Function: It saves the content of VPD first before perform the test. After it is done, it writes one of the five pattern test data, 0xff, 0xaa, 0x55, increment data, or decrement data, into VPD memory. By default, increment data pattern is used. It writes and reads back the data for the entire test range, and then restores the original content.

Default: Disabled

C6. Alert Standard Format (ASF) Test

1. Reset test.

   Setting reset bit, poll for self-clearing. Verify reset value of registers.

2. Event Mapping Test

   Setting SMB_ATTN bit. By changing ASF_ATTN LOC bits, verify the mapping bits in TX_CPU or RX_CPU event bits.

3. Counter Test

C7. ROM Expansion Test

Function: This function tests the ability to enable/disable/access the expansion ROM on the device.

D1. Mac Loopback Test

Function: This is internal loopback data transmit/receive test. It initializes MAC into internal loopback mode, and transmits 100 packets. The data should be routed back to receive channel and receive by the receive routine, which verifies the integrity of data. One Gigabit rate is used for this test.

Default: Enabled

D2. Phy Loopback Test

Function: This test is same as D1. Mac Loopback Test except, the data is routed back via physical layer device. One Gigabit rate is used for this test.

Default: Enabled

D3. RJ45 Loopback Test

D4. MII Miscellaneous Test

Function: This function tests the auto-polling and phy-interrupt capabilities.

Default: Enabled

D5. MSI Test

Function:

Default: Disabled

 

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Error Messages

/* 0 */ 	"PASS",
/* 1 */ 	"Got 0x%08X @ 0x%08X. Expected 0x%08X",
/* 2 */ 	"Cannot perform task while chip is running",
/* 3 */ 	"Invalid NIC device",
/* 4 */		"Read only bit %s got changed after writing zero at offset 0x%X",
/* 5 */ 	"Read only bit %s got changed after writing one at offset 0x%X",
/* 6 */ 	"Read/Write bit %s did not get cleared after writing zero at offset 0x%X",
/* 7 */		"Read/Write bit %s did not get set after writing one at offset 0x%X",
/* 8 */ 	"BIST failed",
/* 9 */ 	"Could not generate interrupt",
/* 10 */ 	"Aborted by user",
/* 11 */ 	"Tx DMA:Got 0x%08X @ 0x%08X. Expected 0x%08X",    
/* 12 */ 	"Rx DMA:Got 0x%08X @ 0x%08X. Expected 0x%08X",    
/* 13 */ 	"Tx DMA failed",
/* 14 */ 	"Rx DMA failed",
/* 15 */ 	"Data error, got 0x%08X at 0x%08X, expected 0x%08X",
/* 16 */ 	"Second read error, got 0x%08X at 0x%08X, expected 0x%08X",
/* 17 */ 	"Failed writing EEPROM at 0x%04X",
/* 18 */ 	"Failed reading EEPROM at 0x%04X",
/* 19 */ 	"EEPROM data error, got 0x08X at 0x04X, expected 0x%08X",
/* 20 */ 	"Cannot open file %s",
/* 21 */ 	"Invalid CPU image file %s",
/* 22 */ 	"Invalid CPU image size %d",
/* 23 */ 	"Cannot allocate memory",
/* 24 */ 	"Cannot reset CPU",    
/* 25 */ 	"Cannot release CPU", 
/* 26 */ 	"CPU test failed",       
/* 27 */ 	"Invalid Test Address Range\nValid NIC address is 0x%08X-0x%08X and exclude 0x%08X-0x%08X",
/* 28 */    "DMA:Got 0x%08X @ 0x%08X. Expected 0x%08X", 
/* 29 */   	"Unsupported PhyId %04X:%04X",
/* 30 */   	"Too many registers specified in the file, max is %d",
/* 31 */ 	"Cannot write to VPD memory",
/* 32 */ 	"VPD data error, got %08X @ 0x04X, expected %08X",
/* 33 */ 	"No good link! Check Loopback plug",
/* 34 */ 	"Cannot TX Packet!", 
/* 35 */ 	"Requested to Tx %d. Only %d is transmitted",       
/* 36 */	"Expected %d packets. Only %d good packet(s) have been received\n%d unknown packets have been received.\n%d bad packets have been received.",
/* 37 */ 	"%c%d is an invalid Test",
/* 38 */ 	"EEPROM checksum error",
/* 39 */ 	"Error in reading WOL/PXE",
/* 40 */ 	"Error in writing WOL/PXE",
/* 41 */ 	"No external memory detected",
/* 42 */ 	"DMA buffer %04X is large, size must be less than %04X",  
/* 43 */ 	"File size %d is too big, max is %d",
/* 44 */ 	"Invalid %s",
/* 45 */ 	"Failed writing 0x%x to 0x%x",
/* 46 */ 	"",
/* 47 */ 	"Ambiguous command",
/* 48 */ 	"Unknown command",
/* 49 */ 	"Invalid option",
/* 50 */ 	"Cannot perform task while chip is not running. (need driver)",
/* 51 */ 	"Cannot open register define file or content is bad",
/* 52 */ 	"ASF Reset bit did not self-cleared",
/* 53 */ 	"ATTN_LOC %d cannot be mapped to %cX CPU event bit %d",
/* 54 */ 	"%s Register is not cleared to zero after reset",
/* 55 */ 	"Cannot start poll_ASF Timer",
/* 56 */ 	"poll_ASF bit did not get reset after acknowledged",
/* 57 */ 	"Timestamp Counter is not counting",
/* 58 */ 	"%s Timer is not working",
/* 59 */ 	"Cannot clear bit %s in %cX CPU event register",
/* 60 */ 	"Invalid "EEPROM_FILENAME" file size, expected %d but only can read %d bytes",
/* 61 */ 	"Invalid magic value in %s, expected %08x but found %08x",
/* 62 */ 	"Invalid manufacture revision, expected %c but found %c",
/* 63 */ 	"Invalid Boot Code revision, expected %d.%d but found %d.%d",
/* 64 */ 	"Cannot write to EEPROM",
/* 65 */ 	"Cannot read from EEPROM",
/* 66 */ 	"Invalid Checksum",
/* 67 */ 	"Invalid Magic Value",
/* 68 */ 	"Invalid MAC address, expected %02X-%02X-%02X-%02X-%02X-%02X",
/* 69 */ 	"Slot error, expected an UUT to be found at location %02X:%02X:00",
/* 70 */ 	"Adjacent memory has been corrupted while testing block 0x%08x-0x%08x\nGot 0x%08x @ address 0x%08x. Expected 0x%08x",
/* 71 */ 	"The function is not Supported in this chip",
/* 72 */ 	"Packets received with CRC error",
/* 73 */ 	"MII error bits set: %04x",
/* 74 */ 	"CPU does not initialize MAC address register correctly",
/* 75 */ 	"Invalid firmware file format",
/* 76 */ 	"Resetting TX CPU Failed",
/* 77 */ 	"Resetting RX CPU Failed",
/* 78 */ 	"Invalid MAC address",
/* 79 */ 	"Mac address registers are not initialized correctly",
/* 80 */ 	"EEPROM Bootstrap checksum error",

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